| 摘要 |
<p>A repeater which receives a frame-multiplexed signal, extracts a receiving clock from the signal, and detects a timing of frame synchronization. The receiving clock and a master clock are input into a selector (3), the output of the selector (3) is supplied for frame regeneration through a clock phase gradual shift circuit (4), and the detected timing is supplied for frame synchronization in the regenerated frame-multiplexed signal through a gate (7). Normally, the receiving clock and the detected timing is supplied for the frame regeneration, however, when the detection of the timing of frame synchronization fails, the output of the selector (3) is switched to the master clock and the gate becomes off, and when the detection of the timing of frame synchronization is recovered and the detected timing of frame synchronization and a timing of frame synchronization in regeneration, which is generated from the master clock, coincide, the output of the selector (3) is switched back to the receiving clock and the gate (7) simultaneously becomes on. Further, in the clock phase gradual shift circuit (4) normally, an output clock synchronizes with an input clock, and a phase shift resulting from an abrupt phase shift occurring in the input clock gradually appears in an output clock after the abrupt phase shift in the input clock.</p> |
