| 摘要 |
PURPOSE:To reduce the synchronizing lock time by deciding whether or not a data pattern in the midway of one frame is coincident with a frame synchronizing pattern while being shifted by one bit each and continuing the dissidence even when the result of succeeding decision shows coincidence if the result of decision is dissident. CONSTITUTION:A frame synchronizing pattern deciding device 21 discriminates whether or not a pattern of an input data is coincident with a built-in frame synchronizing pattern by utilizing the input clock while shifting the pattern one by one bit each and comparing them and outputs the result of discrimination to a controller 31. When the dissidence of a data pattern is inputted to a terminal F of the controller 31 from the frame synchronizing pattern deciding device 21, an F-counter 42 is reset and a mark X is written in an address 1 (address corresponding to bit location 1 and abbreviated hereafter as SR1) of a shift register SR 51. In this case, the mark X remains in the bit location having once written as X even if coincidence takes place afterward. Since the pointer is shifted by looking for the content of the SR to seek the location of the frame synchronizing patter, the time to be shifted to the normal position is decreased thereby reducing the synchronizing lock time. |
