Apparatus and method for performing digital signal processing including fast fourier transform radix-4 butterfly computations.

摘要

A digital array signal processor and associated method are described for implememting the fast Fourier transform radix-4 butterfly algorithm. The digital array signal processor is an integrated circuit with a four stage pipeline and can perform a radix-4 butterfly operation on four complex operands every 80 nanoseconds. Using the decimation-in-frequency implementation of the radix-4 butterfly algorithm, the digital array signal processor includes a first stage for distribution of complex input operand values, a second stage for performing addition and subtraction operations, a third stage for performing multiplication operations and a fourth stage for distribution of the output operand values. The digital array signal processor can be reconfigured to perform a radix-2 butterfly operation on two sets of two complex numbers during the 80 nanosecond machine cycle. The digital signal array processor can be configured to perform a series of operations on an array of operands or can be one of a series of processors, each processor performing a separate operation on an operand array.