CMOS PROGRAMMABLE LOGIC ARRAY

摘要

A programmable logic array includes a dynamic AND plane, and an OR plane using clocked load devices (M17...M20). The high precharge voltage state in the AND plane places the logic lines in the OR plane (00...03) in a lowvoltage state during precharge. The OR logic lines may then be pulled to a high level during the decode operation. A single clock having a delay path (AR) may be used to control the precharge and decode operations of the PLA.