发明名称 FRAME SYNCHRONIZING CIRCUIT
摘要 PURPOSE:To suppress the increase of hard quantity even to the repeating signal of a specified fixed pattern and to execute synchronous leading-in without tail by providing a memory to store the generating condition of a coincident signal and a dissident signal instead of a counter to count these signals. CONSTITUTION:Whether the condition of a frame bit is satisfied in correspondence to respective bit positions or not is checked by plural synchronization detecting parts 1 and the generating condition of the coincident signal and dissident signal, which are outputted from the correspondent synchronization detecting part 1, is stored in plural memory parts 2. How different bit number is from the generating condition of the coincident signal and dissident signal to be expected to the frame bit position for the contents of the correspondent memory part 2 is detected by plural difference detecting parts 3. Then, a deciding part 4 receives all the outputs of the difference detecting parts 3 and decides whether the difference is over one constant or not in the other bit position excepting for one bit position. Thus, even to the repeating signal of the specified fixed pattern, the increase of the hard quantity is suppressed and the synchronous leading-in can be executed without fail.
申请公布号 JPH01194535(A) 申请公布日期 1989.08.04
申请号 JP19880016882 申请日期 1988.01.29
申请人 NEC CORP;NEC TELECOM SYST LTD 发明人 SHIRAI KAZUHIKO;FUKAZAWA YASUO
分类号 H04J3/06;H04L7/08 主分类号 H04J3/06
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