| 摘要 |
PURPOSE:To save the capacity of ROM by obtaining a timing pulse repeated in horizontal direction and a timing pulse repeated in vertical direction by separate ROMs respectively. CONSTITUTION:The circuit is provided with a 1st address counter 651 controlled by a 1st reference pulse in the horizontal period, a 1st ROM 652 whose readout address is controlled by an output of the 1st address counter 651, a 2nd address counter 691 controlled by a 2nd reference pulse having a frequency sufficiently higher than the horizontal frequency, a 2nd ROM 692 whose readout address is controlled by the output of the 2nd address counter 691. Then the timing pulse is obtained from the 1st and 2nd ROM 652, 692. Thus, the memory capacity is reduced. |
