EXAMINATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT,申请号JP19870333572-传众专利搜索

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发明名称	EXAMINATION METHOD FOR SEMICONDUCTOR INTEGRATED CIRCUIT
摘要
申请公布号	JPH01169938(A)	申请公布日期	1989.07.05
申请号	JP19870333572	申请日期	1987.12.24
申请人	SHARP CORP	发明人	ISHITSUKI NORIYOSHI
分类号	G01R31/28;G11C29/00;G11C29/44;H01L21/66;H01L21/822;H01L21/8247;H01L27/04;H01L29/78;H01L29/788;H01L29/792	主分类号	G01R31/28
代理机构		代理人
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