| 摘要 |
PURPOSE:To obtain a phase comparator having a simple and broad utilizing range, by coupling two storage circuits operating in synchronization with two different phase clock pulses in series via an exclusive OR circuit so as to take an output of the storage circuit of the final stage as a comparison output. CONSTITUTION:A clock pulse phi1 is inputted as an input pulse to an FF1, and an output Q1 and input data are inputted to the exclusive OR circuit 3. An output D2 of this circuit 3 is inputted to an FF2 and a clock pulse phi2 is inputted to the clock input of the FF2. Further, the FF2 transmits a comparison output PCM and has a clear input CLR. The phase of the two clock pulses phi1 and phi2 is different from each other. When the phase of the input data does not exist between the timing of the pulses phi1 and phi2, the input data is inputted in synchronization with the timing of the pulse phi1 with the FF1. This output Q1 and the input data are inputted to the circuit 3 and an exclusive OR output D2 is outputted. |
