| 摘要 |
PURPOSE:To set an optional number of modes with only one external terminal by providing a data shifting means which shifts input data and a decoding means which decodes latch data of each latch means to generate plural test mode signals. CONSTITUTION:Three one-bit latch circuits 11-13 are cascaded to constitute a three-bit data shift circuit 14 which shifts data of a terminal 10 successively, and the output of an AND gate 15 to which a shifting clock signal SCK and a reset signal RST are supplied in parallel is supplied to a synchronizing signal terminal. Eight AND gates 160-167 are provided which decode the output of the data shift circuit 14 to generate eight mode signals M0-M7, and signals where Q output signals different from one another of three one-bit latch circuits 11-13 are combined are supplied to these AND gates 16 in parallel. |
