| 摘要 |
<p>A planarization process and the resulting structure are disclosed. Dielectric layers (22/24) are successively deposited over nonplanar first level contacts (18/20) and patterned to form interlevel vias where interconnect plugs to first level contacts are desired. A conductive layer (36) which fills the vias conformally is covered with a photoresist layer (38). The layers (38, 36, 24) are then etched at substantially the same rate to provide planarized contact plugs (28) which are planar with the interlevel dielectric (22/24).</p> |
