| 摘要 |
<p>1. A multifunction pre-diffused array formed in silicon wafers by means of the CMOS technology and provided with polysilicon gate electrodes and at least two levels of metallization, of the type comprising a plurality of rows (13) separated by wiring bays (14), said array being characterized in that : each row includes a plurality of adjacent logic circuits that are not isolated from one another by isolation transistors ; each logic circuit is comprised of a whole number of basic cells (12) the constant granularity M of which, as defined by the whole number of pairs of transistors contained in the cell, is such that the expression N* PM2-M* PPoly, where N is an integer, PPoly is the intra-cell pitch of the polysilicon gate electrodes, and PM2 is the pitch of the second level metallization grid, will take on a minimum yet positive value ; and the first and last diffusion regions, which function as either source or drain, in each circuit are at ground potential (GD) in the case of N-channel transistors and at the supply potential (VH) in the case of P-channel transistors.</p> |
