| 摘要 |
PURPOSE:To cut down the time period of the development.manufacture required for customized formation by a method wherein transistor element formation, contact hole formation, the first layer wiring formation and through hole formation are classified as the master slice while the basic cell is provided with the logical function only by the formation of the second layer wiring. CONSTITUTION:An input signal A is connected to the gate electrodes 101, 105 of P-chTr and N-chTr through the intermediary of the second layer wiring 121-the first layer wiring elements 128a, 128b. P<+>diffused regions 109, 111 are connected to VDD power supply line 117 to be a source of P-chTr by the second layer wirings 124, 126 and the first layer wiring elements 131a, 131b. Said procedures are applicable, likewise, to N-chTr. A P<+> diffused region 110 is connected to the second wiring 123 through the intermediary of the first wiring element 132a while N<+> diffused region 115 is connected to the second layer wiring 123 through the intermediary of the first layer wiring element 132b. Furthermore, gate electrodes 103, 107 are connected respectively to VDD power supply line 117 and VCC power supply line 118 by the first layer wiring elements 130a, 130b and the second layer wiring 126, 127. Through these procedures, two input NAND gate can be constituted. |
