| 摘要 |
<p>A FIFO (first in first out) control circuit (111) for providing address information to a FIFO memory (112). Two up counters (117,118) are used; one to provide the write address and one to provide the read address. A multiplexer (119) selects which addresses (read or write) are used. Two comparators (126,127) along with a simple logic circuit provide two status output signals; namely full (or not) and empty (or not).</p> |
