| 摘要 |
<p>PURPOSE:To shorten the processing time of a unit as a whole by simultaneously executing trend component eliminating processing and FFT processing. CONSTITUTION:A 1st butterfly arithmetic circuit 4, by using the gradient (a) and the intercept (b) of a linear trend component obtained by a trend component decision circuit 3, applies a butterfly arithmetic operation to a signal to be analyzed stored in a memory 2. A butterfly arithmetic circuit 5, applies a butterfly arithmetic operation without using a trend (a) and a cut piece (b) of a liner trend component derived by a trend component deciding circuit. A bit reversal circuit 6 inversely reads out the address bits of data in final step calculated and outputted by the circuits 4, 5 and rearranges the data addresses. As a result, trend composite eliminating processing and FFT processing an be achieved concurrently, and the processing time of the unit as a whole can be shortened.</p> |
