| 摘要 |
Field of application of the invention includes digital satellite sound broadcast receivers and receivers for digital transmission links, the signals of which have a periodic frame structure. The original data rate is halved by a single-bit demultiplexer 1 connected ahead of the main frame synchronisation circuit 8. A bit synchronisation circuit 6 corrects the bit phase errors occurring during this process. It is composed of a correlator 2, a delay device 3, a data selector 4 and a control logic circuit 5. The control logic circuit 5 operates the control device of the data selector 4 in dependence on the correlation result. The circuit arrangement operates with low power dissipation and is suitable for large-scale integration with low dynamic requirements for the level of technology. <IMAGE> |
