| 摘要 |
PURPOSE:To always obtain optimum phases of a clock and data by comparing a phase difference between a demodulated signal and a signal latched by a clock. CONSTITUTION:A demodulated signal is applied to a resonator 2 through a gate 1. The resonator 2 extracts a clock component from the digital signal and a comparator 3 shapes the extracted component to form a reference input to a PLL 4. The demodulated digital signal and the output of a latch 5 are inputted to a phase comparator 6 and an error signal corresponding to a phase difference between two input signals is outputted. The output is smoothed by a low pass filter 7, amplified by an amplifier 8 and its output is applied to the resonator 2 as a control voltage. Consequently, the phase difference between the input data of the latch 5 and the clock is always set up to 90 deg.. |
