| 摘要 |
PURPOSE:To perform direct memory access (DMA) at a transfer speed most suitable for each device by switching a clock signal frequency given to a DMA controller in accordance with the device serving as a DMA transfer object. CONSTITUTION:Clock signals CLK1-CLK3 corresponding to transfer speeds of a memory device 5, I/Os 6a-6c, etc., serving as the data transfer object device are inputted to a clock signal frequency switching part 7. Signals CLK 1-CLK3 are switched by the output of a data transfer object device selecting part 8 in accordance with the transfer speed of the device of DMA and are inputted to a DMA controller 4 from the switching part 7. Thus, the clock signal is sent in accordance with the transfer speed most suitable for each device to always transfer data between devices at the highest speed by the DMA. |
