发明名称 HIGH-SPEED CONTROLLING METHOD OF TERMINAL DEVICE
摘要 PURPOSE:To apply a writing request from a processor at the access speed of a memory part and to shorten the access time to a terminal device, by connecting a terminal controlling device between the terminal device and the processor and incorporating the memory part storing scanned results in the controlling devide. CONSTITUTION:The terminal controlling device 2 is connected between a processor 1 and a terminal device 3 and the device 2 is provided with a memory bus interface part 2a connected to a memory bus connected to the device 1 and a terminal device interface part 2b. A self-scanning part 3c scanning the state of the device 3 while being controlled by itself and a memory part 2d storing the scanned results are also incorporated in the device 2. A writing request is applied from the processor 1 to the device 2 at the memory access speed and then the state of the device 3 is read out from the memory part 2d at the memory access speed. Consequently, the access time to the device is shortened and high- speed processing can be attained.
申请公布号 JPS5945529(A) 申请公布日期 1984.03.14
申请号 JP19820155724 申请日期 1982.09.06
申请人 NIPPON DENKI KK 发明人 NAKAZATO YOSHINOBU
分类号 G06F13/12;G06F3/00;(IPC1-7):06F3/00 主分类号 G06F13/12
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