发明名称 |
Arithmetic and logic circuit stage |
摘要 |
A circuit for performing operations on two bits (A,B), including the processing of a carry from a preceding circuit ( &upbar& C) and transmitting it to a subsequent circuit ( &upbar& C). The circuit includes a network which is formed by MOS transistors which can be programmed via programming lines and which supplies a logic combination. An exclusive carry-propagation-generation device is formed by three MOS transistors which are connected in series between a carry-propagation line and ground and whose gates are connected to one of the bits to be processed, to the logic combination, and to a carry inhibit line, respectively.
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申请公布号 |
US4805130(A) |
申请公布日期 |
1989.02.14 |
申请号 |
US19870030946 |
申请日期 |
1987.03.26 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
LANFRANCA, MICHEL J.;LABROUSSE, JEAN-MICHEL J.;DENEUCHATEL, CHRISTIAN M. |
分类号 |
G06F7/501;G06F7/50;G06F7/503;G06F7/506;G06F7/507;G06F7/508;G06F7/544;G06F7/575;(IPC1-7):G06F7/50 |
主分类号 |
G06F7/501 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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