发明名称 LOGICAL SIMULATION METHOD
摘要 PURPOSE:To simplify a gate and to reduce the number of elements by transforming a transfer switch to a general primitive such as an AND or an OR. CONSTITUTION:A file 101 including logical connecting information is compiled 201, thereafter, the N-MOS type or the P-MOS type wired connecting part circuit of the transfer switch is extracted by a part circuit extracting processing 202 to form file 102 and store the connecting information except it in a file 103. The N-MOS type or the P-MOS type wired connecting information of the transfer switch in the file 102 is transformed to an AND-OR logic according to the general primitive transforming processing A1. Thereby, a logical operation is correctly executed, the number of the elements is reduced and the simplifying processing of the circuit can be applied.
申请公布号 JPS6431260(A) 申请公布日期 1989.02.01
申请号 JP19870189113 申请日期 1987.07.28
申请人 NEC CORP 发明人 GOTO KAZUNAGA
分类号 H03K19/00;G06F17/50;G06F19/00 主分类号 H03K19/00
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