| 摘要 |
<p>PURPOSE:To receive an acknowledge signals at a reception side, by outputting the request clock signal of the acknowledge signal from a CPU via an internal bus after completing the data transmission of a shift register by providing a flip-flop. CONSTITUTION:A clock output flip-flop 22 is provided which sets an internal clock CK and a signal (h) from the CPU via the internal bus 20 as input I1 and I2, respectively, and outputs the input CK and (h) selectively by a control signal phi2 inputted from the CPU separately and a control signal phi3 that is the Q-output of the flip-flop 19. And after the data transmission of the shift register is completed, a control pulse is outputted via the internal bus and the clock output flip-flop. In such a way, it is possible to receive the acknowledge signal at the reception side.</p> |
