| 摘要 |
<p>PURPOSE:To continue the operation of a signal processing circuit of the post- stage by detecting that the pulse density of an input signal is decreased so as to send an output signal of a built-in oscillation circuit as a clock signal thereby preventing missing of a clock. CONSTITUTION:When a conventional 4B5B coded signal of 125Mb/s is given to an input terminal 1, a stable clock signal of 125MHz is extracted from a tank circuit 4. Then an output of a limiter amplifier 5 is selected by a changeover circuit 10, and a data signal and a clock signal in the synchronized state are sent from a data output terminal 3 and a clock output terminal 15 respectively. When the line is idle, the input signal is a repetitive signal of 2.5MHz. Thus, the circuit 4 cannot extract the clock component and an output voltage of a peak detection circuit 6 is decreased. In setting a reference voltage circuit 8 so as to invert the output of a comaprator circuit 7, the circuit 10 sends an output signal of an oscillation circuit 9 to the terminal 15.</p> |
