| 摘要 |
PURPOSE:To set selectively the phase of each distribution output by an initial setting data by outputting a clock inputted as it is or while its phase is retarded in response to the output of a phase selection flip-flop (FF). CONSTITUTION:A NAND gate 7 has a switching function to output a signal with slightly retarded phase or a fixed level 1 and an output of a gate 3 corresponding to the output of the gate 7 is given to a gate 10, from which clock outputs C1-C16 are given. 16-Set of FFs 20 output a clock of a normal phase as clocks C1-C16 or output a clock retarded by a phase corresponding to one stage of gate. The FFs 20 are controlled by a clock input C and the shift mode input (m) and its setting is implemented as part of the initial value setting. Thus, even when the delay time excess is caused, the phase of each clock is adjusted by changing the setting of the output of the phase selection FFs 20. |
