| 摘要 |
PURPOSE:To contrive the improvement of the efficiency by connecting a line adaptor incorporating a buffer memory to a data bus so as to relieve the load of the data bus. CONSTITUTION:A processor PU 3, plural line adaptors 1-0-1-7 and an interface control section IFC 2 are connected by a data bus 100 and a microinstruction of a processor 3 is stored in a control memory 4. Then the line adaptors 1-0-1-7 each composed of a buffer memory, a transmission address register, a reception address register, a transmission byte counter and a reception byte counter, accommodate one line of the HDLC procedure respectively. Moreover, the buffer memory, the transmission/reception address register and the transmission/ reception byte counter are enabled to be read or written by the IFC 2 and the PU 3 via the data bus 100. The load of the data bus is relieved and the efficiency is improved.
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