发明名称 Method of making vertical inverter
摘要 One embodiment of the present invention includes a vertical inverter. A layer of P-type material is formed on the surface of an N+-type substrate, followed by formation of an N+ layer, a P+ layer, an N- layer and a P+ layer. (Of course different doping configurations may be used and remain within the scope of the invention.) A trench is then etched along one side of the stack thus formed and a connector is formed to the middle P+ and N+ layers. Another trench is then formed where a gate insulator and a- gate are formed. The gate serves as the gate for both the N-channel and P-channel transistors thus formed.
申请公布号 US4788158(A) 申请公布日期 1988.11.29
申请号 US19880156128 申请日期 1988.02.16
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 CHATTERJEE, PALLAB K.
分类号 H01L27/092;H01L29/49;H01L29/78;(IPC1-7):H01L27/06;H01L21/36 主分类号 H01L27/092
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