| 摘要 |
PURPOSE:To attain small size and law power consumption of the titled circuit while applying highly accurate level conversion by decreasing a power voltage of a digital IC so as to suppress the DC bias fluctuation relatively with respect to an IF signal level. CONSTITUTION:A voltage of 1.5V(Vcc/2) being a logical threshold value of a digital inverter 8.4 is applied by resistors 8.2, 8.3 as an IF signal whose amplitude is attended with level fluctuation and converted into digital signals of logic levels 0(V),3(V) by the digital inverter 8.4. Moreover, the logic signal is converted into digital signals whose logic is 0(V) and 5(V) respectively by a digital inverter 8.5. Thus, the logic output uncertainty width of the digital inverter 8.4 is decreased, the amplitude of the IF signal is less, and even when the amplitude is fluctuated, the frequency fluctuation at the logic conversion from the analog IF signal into the digital signal is suppressed. |
