| 摘要 |
A decoder circuit fabricated in an IC memory chip and provided to respective word-lines and respective bit-lines of an IC memory matrix fabricated in the IC memory chip, is provided for selecting an EPROM cell which is placed on an intersection point of the word-line and the bit-line, to program a datum into the EPROM cell by using a high power supply voltage when the decoder circuit operates under a programming mode and to read out a datum stored in the EPROM cell by using a low power supply voltage when the decoder circuit operates under a reading mode, receiving an address signal from the exterior of the decoder circuit. The decoder circuit comprises a NAND gate having its load and a CMOS invertor. In making the load of the NAND gate function as a constant current load, only a variable power supply voltage, which becomes a high and a low voltage according to the programming and the reading mode respectively, can be applied to the decoder circuit without using other elements such as a transfer gate and a compensator as required in the prior art.
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