Device for relocking one or a number of identical or submultiple binary data signal trains on a synchronous reference clock signal

摘要

The relocking device comprises a polyphase clock signal generator for producing n clock signals which are equally displaced in phase with respect to each other including the reference clock signal, and rephasing circuits each assigned to one data train to be relocked and each having the function of selecting that version of the clock signal which is most effectively locked with respect to the data train to be processed by means of a double-sampling circuit and a clock-signal selecting circuit addressed by a sequential scanning circuit controlled by a comparator. The rephasing circuits utilize said version for sampling precise values of the data contained in the data train concerned and regenerate said data train by resampling these values in synchronism with the reference clock signal.