| 摘要 |
<p>PURPOSE:To decrease the hardware quantity by using the count value of the oscillation output of an oscillator as an address to read the binary data corresponding to said count value out of a memory means and transmitting the binary data to a central arithmetic processor as a time synchronizing signal. CONSTITUTION:A counter circuit 12 counts the outputs of the time LSI basic clocks 101 received from an oscillator 11 and a memory 13 sends the data corresponding to the address shown by the circuit 12 to a latch circuit 15. In this case, the contents of the memory 13 are incorporated previously by a program that decides the data delivered by the count value of the circuit 12. The circuit 15 latches the output data supplied from the memory 13 for each output of the clock 101 and outputs a time synchronizing signal to a central arithmetic processor 2. The processor 2 replaces the time with input of the signal 102. Thus the hardware quantity can be decreased.</p> |
