| 摘要 |
<p>A high speed memory access circuit of a CRT display unit generates address signals from a memory cycle controller (20) based on an external write signal provided from the exterior and supplies the address signals to a frame memory (8) structured by dynamic random access memories (81 to 86). The frame memory (8) reads out, based on the address signals, the first and the second data in parallel, each data being divided into odd number region data and even number region data. The odd number region data and even number region data of the first data are provided in series through shift registers (313, 323), respectively and the odd number region data and even number region data of the second data are provided in series through shift registers (314, 324), respectively. Thus, the first and the second data read out from the frame memory (8) are provided in series respectively in the form divided into odd number data and even number data and accordingly, it is made possible to employ shift registers of relatively low speed even in case a pattern of a high resolution is displayed by using a non-interlace CRT display unit of 60 Hz.</p> |
