| 摘要 |
PURPOSE:To prevent the change in a pulse width from being caused with a wide phase compensation range by providing a 2nd latch means fetching an output of a 1st latch means fetching a phase control signal synchronously with a retarded clock signal and using an output of the 2nd latch means as a write signal. CONSTITUTION:The 1st latch means fetching plural phase control signals being the result of a 1st decision of a write compensation deciding means 1 synchronously with the same clock signal, a clock delay means retarding the clock signal sequentially by the phase compensation period and generating plural delay clock signals, and the 2nd latch means fetching the plural outputs of the 1st latch means synchronously with the retarded clock signal are provided, and the output of the 2nd latch means is used as a writ signal subjected to phase compensation. That is, DF/F 20-22 constitute a 1st holding means and DF/F 23-25 constitute the 2nd latch means. Moreover, delay elements 26-28 constitute a clock delay means. Thus, the range of phase compensation is set nearly by one clock period.
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