发明名称 |
Semiconductor memory device having initialization transistor |
摘要 |
A memory circuit 14 comprises a MOS transistor 15 having its threshold voltage selected to be higher than the output voltage on the occasion of the ordinary operation. Consequently, the MOS transistor 15 is off on the occasion of the ordinary operation, and a ratio latch 4 performs the ordinary storing operation. Meanwhile, if the output voltage of the power source 12 is raised, the MOS transistor 15 turns on to pull down the potential of a data input line 6a to the ratio latch. Accordingly, the ratio latch 4 is forced to be set.
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申请公布号 |
US4777623(A) |
申请公布日期 |
1988.10.11 |
申请号 |
US19860869653 |
申请日期 |
1986.06.02 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
SHIMAZU, YUKIHIKO;TERAOKA, EIICHI |
分类号 |
G11C7/00;G06F1/24;G11C11/401;G11C11/41;H03K3/037;H03K3/356;(IPC1-7):G11C7/00;G11C11/40 |
主分类号 |
G11C7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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