| 摘要 |
PURPOSE:To highly integrate a semiconductor integrated circuit device against a software error and adapted for high speed operation with low power consump tion by forming a reverse conductivity type semiconductor region under the semiconductor region of a circuit element of the semiconductor region or periph eral circuit for forming a memory cell circuit element. CONSTITUTION:A DRAM memory cell is composed of a series circuit of a switch n-channel MOSFETQs and a capacity element Cp. A buried layer 3 of the same conductivity type as that of a semiconductor substrate 1 and higher impurity concentration is formed between the substrate 1 and an epitaxial layer 2 under the memory cell. Thus, a potential barrier is formed for minority carrier generated in the substrate 1 under the MISFETQs or the element Cp by minority carrier and alpha-ray implanted from an n<+> type semiconductor region disposed in the vicinity to the substrate by the operation of a parasitic bipolar transistor. Accordingly, it can prevent the minority carrier from invading to the memory cell. Thus, an access time can be accelerated, and it can prevent a software error, and improves its electric reliability. |
