PROGRAMMABLE WORD LENGTH AND SELF-TESTING MEMORY IN A GATE ARRAY WITH BIDIRECTIONAL SYMMETRY

摘要

PROGRAMMABLE WORD LENGTH AND SELF-TESTING MEMORY IN A GATE ARRAY WITH BIDIRECTIONAL SYMMETRY The ease and versatility by which logic functions may be implemented in a semicustom CMOS gate array is substantially increased by disposing core cells (62, 67) within the gate array about a plane (18) of mirror symmetry. Such a gate array is devised with mirror symmetry in two orthogonal directions. A memory design of general utility and with particular utility in a gate array is devised so as to operate with a programmable word length. The word length of the memory is programmed by choosing an appropriate integrated circuit metal mask option to be utilized in the memory circuit design at a data bus input and output mapping. In the event that the memory is entirely included within a large scale integrated circuit, such as a gate array, a circuit design is further devised for providing a self-test of the operability of such a fully included memory without the necessity of providing input/output pins communicating with the memory (70) or other external test signals. The self-test is activated by applying a single external start signal at a corresponding single external circuit pin (line 206) with an indication of failure at any point during a complete memory test cycle being coupled to a second external failure pin (208). A self-test protocol is utilized wherein an internal counter (216) generates the addresses of each memory location and stores that address as data within the memory location and the inverse of the address as data. In each case, what was then written into the memory is compared to that which is later read from the memory to thereby validate operability of the memory.