发明名称 SEMICONDUCTOR DEVICE
摘要 PURPOSE:To analyze an internal active element more accurately by including a check pattern formed by annularly shaping a p<+> layer and an n layer in the same process used for forming the internal active element along the end of a chip around the chip. CONSTITUTION:Each pattern of a collector phosphorus n<+> layer 1, a base boron p<+> layer 2, a resistance boron p<+> layer 3 and an emitter n<+> layer 4 annularly surrounds the periphery at intervals (b) along the outsides of pads and the end of a chip. The width (a) of the pattern represents an internal active region and may be shaped in an extent employed as an element, several mum to several dozens of mum, and the intervals (b) of the patterns may be formed in the same extent. When the cross section of the internal active element is analyzed by shaping such patterns, the cross section can be compared and inspected because there is positively said check pattern in a peripheral section even at any position on a chip. Accordingly, accurate analysis is enabled.
申请公布号 JPS63220538(A) 申请公布日期 1988.09.13
申请号 JP19870054616 申请日期 1987.03.09
申请人 NEC CORP 发明人 TSUNEKAWA YASUMASA
分类号 H01L21/66;G01R31/26 主分类号 H01L21/66
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