| 摘要 |
PURPOSE:To relieve the load of the software due to bus control by using a chip select signal and a ready signal from plural processors so as to control the access to a common bus. CONSTITUTION:A common bus control circuit 3 is inserted between local buses 1A, 1B of two processors A, B and a common bus 4. The common bus 3 informs the busy state of the common bus 4 by bringing the ready signal of the processors A, B to a low level and informs the release of the common bus 4 by bringing the ready signal to a high level. When the processor whose bus access is inhibited is going to access the common bus 4, the wait state is kept until the common bus 4 is released automatically. |
