BUS CONTROL ARCHITECTURE FOR MICROPROCESSORS

摘要

A transportable bus control architecture for single-chip microprocessors is disclosed. The bus control architecture consists of an interface control unit that is logically independent of the associated co-resident, common clock-driven microprocessing unit. This independence allows the interface control unit logic to be used with a variety of microprocessing units. Further, the interface control unit presents an external appearance that is compatible with the peripheral devices of a specific microprocessor referred to as the "compatible microprocessor", thereby making available to an associated co-resident microprocessing unit the support devices of the compatible microprocessor. The interface control unit can also access other external devices not related and transparent to the devices of the compatible microprocessor. The interface control unit is logically divided into an execution section and a control section. The execution section is controlled by the control section and comprises various registers, latches, multiplexers, logic, and data and address paths that provide communication between the co-resident microprocessing unit and off-chip devices. The control section of the interface control unit executes commands from the co-resident microprocessing unit and also performs bus arbitration, interrupt, and external reset functions. Bus cycles are of two types: memory- access or service, depending on the command from the co-resident microprocessing unit. Service cycles perform the interrupt acknowledge functions and other sense and control functions requested by the co-resident microprocessing unit. These sense and control functions have the special feature of being pin-programmable and pin-readable by the microprocessing unit. All action initiated by commands from the microprocessing unit elicits a comprehensive status response from the interface control unit.