| 摘要 |
PURPOSE:To access a memory at a high speed by providing registers of the number of operation modes of a CPU, storing a management page part of a physical address which has been brought to address conversion in these registers, and executing cache access by using an output of each register as a part of the physical address in accordance with the operation mode of the CPU. CONSTITUTION:With regard to a register for latching a management page part PA', a first register 31 and a second register 32 of an operation mode portion of a CPU 1, namely, two pieces are provided, and gate circuits g1, g2 for controlling these registers 31, 32 are provided. Also, a first multiplexer MPX 71 for switching the registers 31, 32, and a second multiplexer MPX 72 for switching physical addresses PA from the first MPX 71 and an address converter MMU 2 are provided.
|
