| 摘要 |
PURPOSE:To lower cost and miniaturize a device, by providing (n-1) of data effective bits, and detecting the maximum values of (n)-number of data shift registers with (n-1)-number of comparators. CONSTITUTION:A digital value data 2 of (k)-bits is inputted to an input register 3 at every supplying of a clock pulse 1, and is shifted to the data shift registers 51-54 in order. When a valve 1 is stored in the register 3, since all of the values 61-64 of the data shift register 5 are all 0s, the outputs of the comparators 71-73 show A>B, and all of the values 132-134 of a data effective register 12 are shown as invalid valves. Therefore, an AND gate 81 becomes effective, and a tri-state buffer 91 is opened, and the data 61 of the register 51 is outputted to a maximum stretch data 10. Next, when a value 3 is stored in the register 3, since it is larger than the values of the data 61-63, all of the values show the invalidity of data, then, the data 3 of the register 51 is outputted to a data 10.
|
