发明名称 Memory circuit with improved word line noise preventing circuits
摘要 A memory circuit provided with an improved word line noise preventing circuit is disclosed. The memory circuit is one of the type having a pair of digit lines, a plurality of word lines intersecting with the digit lines, a plurality of memory cells, a sense amplifier coupled to the pair of digit lines and a plurality of noise preventing circuits provided for the word lines. The memory is featured in that the noise preventing circuits are disenabled during the period when the sense amplifier amplifies the voltage difference between the pair of digit lines.
申请公布号 US4764902(A) 申请公布日期 1988.08.16
申请号 US19860880969 申请日期 1986.07.01
申请人 NEC CORPORATION 发明人 MORITA, YASUKAZU
分类号 G11C11/407;G11C8/08;(IPC1-7):G11C11/40;G11C13/00 主分类号 G11C11/407
代理机构 代理人
主权项
地址