| 摘要 |
PURPOSE:To recover a sampling clock with high accuracy without increasing the circuit scale by applying the phase detection based on 1st clock group only and using the 1st and 2nd clock groups in selecting the optimum phase clock and in discriminating the optimum phase. CONSTITUTION:When an integration value (count) of an integration circuit 20 is shown in the figure, a code '00011000' is inputted to address input terminals A0-A7 of an optimum phase discrimination circuit 30. Since the 2nd clock groups CK1, CK3,...,CK15 located among the 1st clock groups CK0, CK2,...,CK14 can be selected, it is possible to select a phase P7 located between phases P6 and P8. Thus, the sampling clock SAS having a double accuracy can be recovered without increasing the circuit scale of an edge detection circuit 10 and the integration circuit 20. |
