发明名称 PROGRAMMABLE LOGIC ARRAY
摘要 PURPOSE:To attain the low power consumption of a programmable logic array (PLA) by constituting the array by CMOS circuits only. CONSTITUTION:A gate electrode 1 is bridged over between a 1st conduction type MOSFET 2 and a 2nd conduction type MOSFET 5 and connected in common and a source electrode 4 of the MOSFET 2 is connected also in common. Two unit arrays 6 are connected back to back to constitute a unit block 7. The unit blocks 7 are connected in parallel to form a unit block group 8 and plural unit block groups 8 are arranged to constitute the 1st basic block 10 and the 2nd basic block 11. Thus, the PLA employing CMOS components only is obtained to reduce the power consumption.
申请公布号 JPS63175522(A) 申请公布日期 1988.07.19
申请号 JP19870007784 申请日期 1987.01.14
申请人 NEC CORP 发明人 FURUKI KATSUYA;SUGIYAMA NOBUYUKI;KITAMURA YOSHINARI
分类号 H03K19/177;H01L21/82;H01L27/118 主分类号 H03K19/177
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