| 摘要 |
PURPOSE:To perform serial data processing without using a high-speed memory nor lowering a data transfer speed by stopping the shifting operation of one S/P converting circuit during the shifting operation of the other and writing held data in a memory. CONSTITUTION:A control circuit 21 generates an operation mode alternation control signal S according to a shift clock CK and supplies it to a NOR gate 23 and to a NOR gate 24 through an inverter 25. Consequently, the outputs of the gates 23 and 24 are fixed at high level alternately as the signal S varies between the high and low levels, the S/P converting circuits 11 and 12 stop shifting operation alternately. Simultaneously, a selector 22 is switched according to the state of the signal S and the held data of an S/P converting circuit which stops the shifting operation is supplied as write data to the buffer memory 13. A memory control circuit 15 supplies an address ADR from an address counter 14 to an address signal line and lowers a write signal W to the lower level to write parallel data from the selector 22 in the memory 13. This writing is performed slower than a write clock speed. |
