| 摘要 |
PURPOSE:To execute all data accesses by selecting a first memory interface bus as a bus for executing the data access when a signal showing that an abnormality is generated in a second memory interface bus is received. CONSTITUTION:While a processor 11 executes a program via the second memory interface bus 6, when the abnormality is generated in the bus 6, a bus abnormality detecting circuit 15 outputs a bus abnormality signal to a bus control circuit 12. In the circuit 12, a request permission signal transmitted to a second memory interface bus control circuit 14 is stopped to output the request permission signal to a first memory interface bus control circuit 13. Thereby, the circuit 13 is controlled so as to execute the memory request from the processor 11 via the first memory interface bus 5. In such a way, the bus 5 or 6 is selected according to the state of the bus and the data access is carried out by one of them, so that all the data accesses can be executed without a difficulty.
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