| 摘要 |
PURPOSE:To contrive the increase of processing speed and the number of tap by operating each circuit interposed between a serial/parallel conversion circuit and a parallel/serial conversion circuit according to 1/N clock with N frequency division of the input clock. CONSTITUTION:The titled filter is constituted of a serial/parallel conversion circuit 1 applying the input sampling string of the parallel processing and outputting a parallel output according to the input clock, an N point inverse high speed Fourier transform circuit 3, N set of sub-filters 40-4N-1 comprising a definite impulse response filters and applying filtering, an N point high speed Fourier transformation circuit 5, and a parallel/serial conversion circuit 6 outputting serially it into the input clock. Thus, a frequency divider circuit 2 sends a I/N clock being 1/N frequency division to the input clock to each circuit ands each circuit is operated according to the I/N clock being the 1/N frequency division of input clock. Thus, even if the speed of the input sampling string is large, the circuit copes easily with it. |
