| 摘要 |
PURPOSE:To reduce the load on each frequency divider and efficiently supply power to each frequency divider and reduce the number of elements to increase the operation speed by interposing a buffer circuit having the level shift function between the frequency divider in the preceding stage and that in the succeeding stage. CONSTITUTION:Buffer circuits 14-having the level shift function are interposed between respective stages of frequency dividers 11, 12- constituted by cascading flip flop (FF) circuits in many stages, and level shift diodes for clock interposed between FF circuits constituting frequency dividers 11, 12- are transferred to buffer circuits 14-. Consequently, level shift diodes for clock constituting respective FF circuits are unnnecessary and the load is reduced from 4a+alpha. (alpha is the wiring capacity for connection to the clock terminal of the following stage) to 2a+beta (beta is the capacity of the interstage buffer). Thus, the load is reduced and the operation speed is increased and the reliability is improved.
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