发明名称 SURFACE SUPERLATTICE MIS TYPE FET
摘要 PURPOSE:To manufacture a surface superlattice MISFET, by forming a first very thin gate electrode whose width is less than or equal to 0.1mum on a part of a gate insulation, and forming a second gate electrode on the other gate region. CONSTITUTION:A diffusion region composed of a source 2 and a drain 3 is formed on the surface of a semiconductor substrate 1, and a gate film 14 is formed on the surface of a region sandwitched by the source 2 and the drain 3. On a part of the surface of the gate film 14, an electrode composed of a gate 15 is very finely formed whose width is less than or equal to 0.1mum. On its surface, a gate film 2 is formed, and thereon an electrode being a gate 27 is formed so as to fill the gate region except the gate 15. By applying a voltage to the gate electrode, a depletion layer or an accumulation layer is formed under the gate 27. An action which generates tunnel effect of electron or hot electron flow is given to this very fine depletion layer or accumulation layer to realize the high speed operation of a MISFET.
申请公布号 JPS63132478(A) 申请公布日期 1988.06.04
申请号 JP19860278200 申请日期 1986.11.21
申请人 SEIKO EPSON CORP 发明人 IWAMATSU SEIICHI
分类号 H01L29/78;H01L29/772 主分类号 H01L29/78
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