| 摘要 |
PURPOSE:To attain to reduce memory capacity and to uniformize the resolving power of an entire region of a measuring range, by accessing a speed converting memory apparatus at every section among sections obtained by predetermined division of a pulse cycle measuring range by a binary pulse cycle detecting signal from which lower rank bits corresponding to the number of sections are eliminated. CONSTITUTION:A pulse generated at every unit movement of a moving body is detected by a detector 1 and a pulse cycle measuring part 2 counts a pulse cycle interval clock to measure a pulse cycle to generate a binary parallel signal. The entire measuring range of this pulse cycle is divided into four sections of which the boundaries are defined by count values 128, 512, 2048, 8192 each being a multiple of two and a predetermined number of lower rank bits of the binary parallel signal outputted by the measuring part 2 are eliminated corresponding to the numbers of the sections to obtain an address signal while ROM7A-7D storing conversion speeds corresponding to the sections are accessed to convert the pulse cycle to a speed. By this constitution, memory capacity for conversion is reduced and the resolving power of the count value becomes uniform over the entire region of the measuring range. |
