| 摘要 |
<p>The bias voltage generator is particularly intended for EPROM memory address decoder circuits, and comprises: (a) a stage generating a reference voltage approximately equal to the turn off threshold voltage of a natural transistor, with its sign changed; and (b) a doubler stage driven by the reference voltage and adapted to supply a bias voltage equal to twice the turn off threshold voltage with its sign changed. Preferably, the bias voltage generator furthermore comprises an adjustment stage driven by the output bias voltage to inject an additional current in negative feedback into said doubler stage when the output bias voltage drops, to return it to the desired value.</p> |
