发明名称 |
Integrated memory circuit having an improved logic row selection gate |
摘要 |
The invention relates to a (static) memory which is divided into a number of memory blocks, memory cells being arranged in rows and columns in each memory block. A row in a memory block is activated via a selection gate whereto there are applied an inverted row selection signal (which is applied to all memory blocks) and a non-inverted and an inverted block selection signal (which is applied to all section gates in a memory block). The selection gate comprises a P-MOS transistor and two parallel-connected N-MOS transistors. The junction between the P-MOS and the N-MOS transistors constitutes the gate output (for activating a row of cells). The row selection signal is applied to the gate electrode of the PMOS transistor and of a first N-MOS transistor. The inverted block selection signal is applied to the gate electrode of the other N-MOS transistor and the block selection signal is applied to the main electrode of the P-MOS transistor.
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申请公布号 |
US4723229(A) |
申请公布日期 |
1988.02.02 |
申请号 |
US19860825842 |
申请日期 |
1986.02.04 |
申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
HARTGRING, CORNELIS D.;LIST, FRANS J. |
分类号 |
G11C11/44;G11C8/00;G11C8/12;G11C11/418;(IPC1-7):G11C11/40 |
主分类号 |
G11C11/44 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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